View ICS8602_4871555.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8602by w w w .icst.com/products/hiperclocks.html re v . f april 1 6 , 2003 1

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary g eneral d escription the ICS8602 is a high performance, low skew, 1-to-9 differential-to-lvcmos/lvttl zero de- lay buffer and a member of the hiperclocks? family of high performance clocks solutions from ics. the clk, nclk pair can accept most standard differential input levels. the vco operates at a fre- quency range of 2 5 0mhz to 500mhz. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clocks. the device is designed only for 1:1 input/output frequency ratios. the output divider allows a wide input/output frequency range with the 2 5 0mhz to 500mhz vco. the pll_sel pin can be used to bypass the pll for system test and debug purposes. in bypass mode, the reference clock is routed around the pll and into the in- ternal output dividers.the low impedance lvcmos/lvttl out- puts are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be doubled by utilizing the ability of the outputs to drive two series termi- nated lines. the differential reference clock input will accept any differential signal levels. b lock d iagram p in a ssignment f eatures ? fully integrated pll ? 9 lvcmos/lvttl outputs, 7 ? typical output impedance ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency range: 15.625 mhz to 250mhz ? input frequency range: 1 5 . 6 2 5 mhz to 250mhz vco range: 2 5 0mhz to 500mhz external feedback for ?zero delay? clock regeneration with configurable frequencies cycle-to-cycle jitter: 36ps (typical) output skew: 125ps (maximum) static phase offset: tbd100ps (typical) 3.3v supply voltage 0c to 70c ambient operating temperature 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v ddo q5 gnd q4 v ddo q3 gnd mr / noe v dda v dd clk nclk gnd div_sel0 div_sel1 gnd gnd q2 v ddo q1 gnd q0 v ddo fb_in gnd q6 v ddo q7 gnd q8 v ddo pll_sel 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ICS8602 the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specifications without notice. hiperclocks? q0 q1 q2 q3 q4 q5 q6 q7 q8 sel0 sel1 clk nclk fb_in pll_sel mr / noe 0 1 pll 2 4 8 16
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 2

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary t able 1. p in d escriptions t able 2. p in c haracteristics t able 3a. c ontrol i nput f unction t able , pll_sel = 1 r e b m u ne m a ne p y tn o i t p i r c s e d 1v a d d r e w o p. n i p y l p p u s g o l a n a 2v d d r e w o p. n i p y l p p u s e r o c 3k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i , 6 1 2 1 , 8 , 5 9 2 , 5 2 , 2 2 , 8 1 d n gr e w o p. d n u o r g y l p p u s r e w o p 7 , 61 l e s _ v i d , 0 l e s _ v i dt u p n in w o d l l u p . 3 e l b a t n i d e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9n i _ b ft u p n in w o d l l u p s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l . " y a l e d o r e z " h t i w , 0 2 , 4 1 , 0 1 1 3 , 7 2 , 4 2 v o d d r e w o p. s n i p y l p p u s t u p t u o , 1 2 , 9 1 , 5 1 , 3 1 , 1 1 0 3 , 8 2 , 6 2 , 3 2 , 4 q , 3 q , 2 q , 1 q , 0 q 8 q , 7 q , 6 q , 5 q t u p t u o 7 . s t u p t u o k c o l c ? . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 1e o n / r mt u p n in w o d l l u p . e l b a n e t u p t u o w o l e v i t c a . t e s e r r e t s a m h g i h e v i t c a d n a t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w e h t , w o l c i g o l n e h w . ) z i h ( d e t a t s - i r t e r a s t u p t u o e h t . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 3l e s _ l l pt u p n ip u l l u p s a k c o l c e c n e r e f e r e h t d n a l l p e h t n e e w t e b s t c e l e s . l l p s t c e l e s , h g i h n e h w . s r e d i v i d e h t o t t u p n i e h t . k c o l c e c n e r e f e r s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r 1 l e s _ v i d0 l e s _ v i d n i f = t u o f ) z h m ( e g n a r y c n e u q e r f m u m i n i mm u m i x a m 00 5 2 10 5 2 01 5 . 2 65 2 1 10 5 2 . 1 35 . 2 6 11 5 2 6 . 5 15 2 . 1 3 l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v , a d d v , o d d v 7 4 . 3 =d b tf p r t u o e c n a d e p m i t u p t u o 7 ? t able 3b. c ontrol i nput f unction t able , pll_sel = 0 pll b ypass m ode 1 l e s _ v i d0 l e s _ v i d r e d i v i d y c n e u q e r f n i ft u o f 00 n i f2 / n i f 01 n i f4 / n i f 10 n i f8 / n i f 11 n i f6 1 / n i f
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 3

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0 c to 70 c t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , 1 l e s _ v i d , 0 l e s _ v i d e o n / r m , n i _ b f v d d v = n i v 5 6 4 . 3 =0 5 1a l e s _ l l pv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i , 1 l e s _ v i d , 0 l e s _ v i d e o n / r m , n i _ b f v d d v , v 5 6 4 . 3 = n i v 0 =5 -a l e s _ l l pv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o d d , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . t i u c r i c t s e t d a o l t u p t u o v 3 . 3 l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 4a m i a d d t n e r r u c y l p p u s g o l a n a 0 1a m i o d d t n e r r u c y l p p u s t u p t u o 0 6 1a m a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 42.1 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4c. d ifferential dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv d d v = n i v 5 6 4 . 3 =0 5 1a k l c nv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i k l cv d d v , 5 6 4 . 3 = n i v 0 =5 -a k l c nv d d v , 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0 + d n gv d d 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . s i k l c n , k l c r o f e g a t l o v m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n v d d . v 3 . 0 +
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 4

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary t able 5. ac c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0 c to 70 c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 2 6 . 5 10 5 2z h m p t h l , y a l e d n o i t a g a p o r p 1 e t o n ; h g i h - o t - w o l z h m 0 , v 0 = l e s _ l l p f z h m 0 5 2d b td b ts n ) ? ( t2 e t o n ; t e s f f o e s a h p c i t a t s , z h m 3 3 1 = f e r f , v 3 . 3 = l e s _ l l p z h m 6 6 2 = o c v f 0 0 1 d b ts p , z h m 0 5 = f e r f , v 3 . 3 = l e s _ l l p z h m 0 0 1 = o c v f 0 0 1 d b ts p t ) o ( k s4 , 3 e t o n ; w e k s t u p t u ov t a e g d e g n i s i r n o d e r u s a e m o d d 2 /5 2 1s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y cv t a e g d e g n i s i r n o d e r u s a e m o d d 2 /6 3s p t l e m i t k c o l l l p 1s m t r e m i t e s i r t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 0 40 5 9s p t f e m i t l l a f t u p t u oz h m 0 5 @ % 0 8 o t % 0 20 0 40 5 9s p c d oe l c y c y t u d t u p t u oz h m 0 5 2 = f0 5% t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n v o d d . 2 / l a n g i s t u p n i k c a b d e e f e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n t a d e r u s a e mv o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 5

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary p arameter m easurement i nformation d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit scope qx lvcmos v dd , v dda , v ddo = 1.65v5% gnd = -1.65v5% c ycle - to -c ycle j itter v cmr cross points v pp gnd clk nclk v dd odc & t p eriod p ropagation d elay o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f t sk(o) v ddo 2 v ddo 2 qx qy o utput s kew nclk clk q0:q8 t pd v ddo 2 s tatic p hase o ffset pulse width t period t pw t period odc = v ddo 2 q0:q8 ? ? ? ? v ddo 2 v ddo 2 v ddo 2 q0:q8 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 t ( ? ) ? ? v dd 2 (where t ( ? ) is any random sample, and t ( ? ) mean is the average of the sampled cycles measured on controlled edges) t ( ? ) mean = static phase offset nclk fb_in clk
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 6

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS8602 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 ? resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. f igure 2. p ower s upply f iltering 10 ? v dda 10 f .01 f 3.3v .01 f v dd v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 7

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary f igure 3c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3d show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 3a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 8

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary r eliability i nformation t ransistor c ount the transistor count for ICS8602 is: 1828 t able 6. ja vs . a ir f low t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8 c/w 55.9 c/w 50.1 c/w multi-layer pcb, jedec standard test boards 47.9 c/w 42.1 c/w 39.4 c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 9

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary p ackage o utline - y s uffix t able 7. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
8602by www.icst.com/products/hiperclocks.html rev. f april 16, 2003 10

ICS8602 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator preliminary t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t y b 2 0 6 8 s c iy b 2 0 6 8 s c ip f q l d a e l 2 3y a r t r e p 0 5 2c 0 7 o t c 0 t y b 2 0 6 8 s c iy b 2 0 6 8 s c il e e r d n a e p a t n o p f q l d a e l 2 30 0 0 1c 0 7 o t c 0

▲Up To Search▲

Price & Availability of ICS8602

	To Download ICS8602 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .